1. Technical Field
The present inventions relate to loopback of signals from a first chip to a second chip and back to the first chip.
2. Background Art
Loopback refers to a process wherein a first chip transmits signals to a second chip and the second chip sends the signals back to the first chip. Loopback is used in analog and digital validation, test, and debug. “Inband” interconnects (conductors) carry inband signals that include data. “Side band” interconnects (also called “out of band” interconnects carry commands, but not the data. The inband signals on the inband interconnects may be packetized to include traditional data with other information such as commands, address (destination), and headers. The signals to be looped back are typically sent from the first chip to the second chip on inband interconnects. When the second chip is in a loop back mode, it transmits all or almost all of the signals back through inband interconnects to the first chip. The inband interconnects carrying the signals back to the first chip may be the same as or different than the inband interconnects that carrying the signals to the second chip.
In prior art techniques, the loopback mode is initiated through loopback initiating signals provided to the second chip through sideband interconnects. Further, the loopback initiating signals are provided to the second chip in response to software, such as an operating system, rather than in response to physical circuitry. Using an operating system to initiate loopback may mask a failure because of error correction. Product validation can be significantly impaired because of a lack of ability to isolate exact failing conditions.
Various techniques have been developed for chips to communicate with each other. The techniques include those that have been standardized and those that have not been standardized. An example of standardized techniques include versions of the Peripheral Chip Interconnect (PCI) Local Bus Specification, such as a PCI Local Bus Specification rev. 2.2, dated Dec. 18, 1998, by the PCI Special Interest Group (SIG). A PCI Express specification, formerly known as 3GIO (3rd generation input output), is in the process of being defined by the PCI SIG. A PCI Express Base Specification Revision 1.0, Jul. 22, 2002, has been released and is available with the payment of a fee.
Signals are often applied differentially on two interconnects. The term “common mode” refers to the average voltage on the interconnects. Systems have used capacitors in series with interconnects to pass the difference between signals on the two interconnects, but not the common mode under ordinary operation. The 8b/10b code is a commonly used code in serial links.